Kwabena Boahen, Ph.D.Professor, Bioengineering and Electrical Engineering, Stanford University
Spike-Based AI Hardware
Deep Neural Networks (DNNs) replace the brain’s spike-trains with instantaneous rates that are updated once every time-step. They have proven to be extremely powerful, successfully tackling tasks that were thought to be impossible just a decade ago. The current quest is to deploy DNNs on devices that communicate by radio and are powered by batteries or harvested energy (e.g., mobile phones or IoT end-points, respectively). These entirely wireless devices—projected to reach 20 billion by 2020—require much more energy-efficient computing platforms. A promising brain-inspired approach, known as neuromorphic computing, maps DNN’s discrete-time rates (functional level) to continuous-time spikes (hardware level), but its potential is yet to be realized.
In spiking neuromorphic hardware, instead of communicating and computing every time-step (clock-driven operation), communicating and computing only happens when a spike occurs (event-driven operation). Thus, communicational and computational load is reduced if each rate-update requires less than one spike (on average). And also if mapping rates to spikes does not degrade performance. Otherwise, the network’s size must be increased to compensate I will argue that spike-based neuromorphic computing’s potential energy-savings can be maximized by exploiting analog computation and communication and I will present my group’s progress in designing these mixed-signal neuromorphic chips and in reducing the overhead incurred mapping DNNs onto them.