Rajeev Alur, Ph.D.

Rajeev Alur is a leading researcher in formal modeling and algorithmic analysis of computer systems. A number of automata and logics introduced by him have now become standard models with great impact on both the theory and practice of verification. His key contributions include timed automata for modeling of real-time systems, hybrid automata for modeling discrete control software interacting with the continuously evolving physical environment, and visibly pushdown automata for processing of data with both linear and hierarchical structure such as XML documents.